1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device manufactured by the damascene process.
2. Description of the Related Art
In recent years, with the improvement in the integration density of the semiconductor device, the miniaturization of the wiring is required. As the method of forming the wiring, there is the method of forming the barrier metal layer on the aluminum film and then forming the aluminum wiring by patterning directly the aluminum film and the barrier metal layer. According to this method, because the etching of the aluminum film progress in the lateral direction during the patterning, not only the wiring width is unnecessarily narrowed, but also the barrier metal layer remains on the aluminum wiring like a pent roof. In this manner, this method has a difficulty in manufacturing a precise wiring and poses a limit on progress in miniaturization of the wiring.
In contrast, in the so-called damascene process, the metal film is not directly patterned as in the above. In stead, the wiring is formed by forming the trench by etching the insulating film and then burying the metal, such as the copper or the like, in this trench. Because the etching object is the insulating film, the above disadvantage does not occur in the damascene process and thus the wiring can be miniaturized as desired. In addition, because the copper wiring having a lower resistance than that of the aluminum wiring can be formed in the damascene process, the operation speed of the semiconductor device can be increased.
The damascene process is roughly classified into two categories, single damascene process and the dual damascene process.
FIG. 19 is a sectional view showing the semiconductor device manufactured by the single damascene process in the prior art. In FIG. 19, reference numeral 3 denotes the first wiring that consists of the barrier metal layer 2 and the metal film 1. Such first wiring 3 is buried in the wiring trench 12a in the insulating film 12.
On the other hand, reference numeral 8 denotes the second wiring that consists of the barrier metal layer 6 and the metal film 7, and is buried in the wiring trench 5a in the upper insulating film 5. This second wiring 8 and the above first wiring 3 are connected electrically via the conductive plug 11 (referred to as the “plug” hereinafter). Such plug 11 has the double-layered structure consisting of the barrier metal layer 9 and the metal film 10, and is buried in the via hole 4a in the lower insulating film 4.
In order to obtain the above structure by the single damascene process, the plug 11 is buried in the via hole 4a after the lower insulating film 4 is formed. Then, the upper insulating film 5 is formed on the lower insulating film 4, and then the wiring trench 5a is formed in the upper insulating film 5. Then, the second wiring 8 connected to the plug 11 is buried in the wiring trench 5a. 
In this manner, because the plug 11 and the second wiring 8 are formed separately in the single damascene process, such a structure is formed that the metal film 10 and the metal film 7 are isolated by the barrier metal layer 6.
On the other hand, FIG. 20 is a sectional view showing the semiconductor device manufactured by the dual damascene process in the prior art. In FIG. 20, the same reference numeral as those in FIG. 19 are affixed to the same constituent members as those in FIG. 19, and their explanation will be omitted hereunder.
In order to obtain this structure by the dual damascene process, the lower insulating film 4 and the upper insulating film 5 are laminated and then the wiring trench 5a and the via hole 4a are formed in these insulating films. Then, the barrier metal layer 13 is formed simultaneously on each inner walls of the wiring trench 5a and the via hole 4a. Then, the plug 11 and the second wiring 8 are simultaneously formed by forming the metal film 14 on the barrier metal layer 13. Both the plug 11 and the second wiring 8 have the double-layered structure of the barrier metal layer 13 and the metal film 14.
In this way, in the dual damascene process, the plug 11 and the second wiring 8 are formed simultaneously. As a result, the plug 11 and the second wiring 8 are not isolated by the barrier metal layer but are formed integrally.
As described above, both the single and dual damascene process can miniaturize the wiring and improve the integration density of the semiconductor device.
Such semiconductor device, however, is still to be improved its stress migration resistance. The stress migration is the phenomena where the metal film 14, in some cases the barrier metal layer 13 as well, is lifted up in the via hole 4a due to the difference in physical constants such as the thermal expansion coefficient, etc. between the metal film 14 and the insulator (the upper insulating film 5 or the lower insulating film 4) to cause the connection failure between the plug 11 and the first wiring 3.
If the stress migration is ready to occur in this manner, the fraction defective increases in the thermal process in the course of the manufacture, which brings about such a disadvantage that the production cost of the semiconductor device increases.